Under several decades of development in semiconductor integrated circuit IC technology, the circuit scale is getting larger, the feature size is getting smaller, and the density of integration is getting higher. In the nanometer scale, short-channel effect of a conventional planar device is getting worse, and is difficult to meet the requirements for the development of integrated circuit technology. A multi-gate device such as a fin field effect transistor (FinFET), as one of substitutes for the planar device, has attracted increasing attention, and has been applied in Intel 22mn technology. FinFET structure in prior art is shown in FIG. 1, comprising substrate 01; source region 06 and drain region 07, which are formed on the substrate and are positioned respectively at both ends thereof; a protruding fin structure 08 and a field dielectric layer 09, which extend between the source region and the drain region on the substrate; a gate dielectric layer 010 on both the fin structure and the field dielectric layer; and a gate electrode 011 over the gate dielectric layer. The multi-gate device usually comprises several parallel-connected fins, where a channel region is formed on each of portions of the fin structure in contact with the gate electrode, that is, the multi-gate device has a plurality of gates, which contributes to enhance of performance of the device. The gate may has a cross-section of various shapes, such as π type, Ω type, quadrilateral shape or cylindrical shape, etc., corresponding to the respective multi-gate devices of FinFET, Tri-gate-FET, Ω-FET, Gate-all-around FET, etc. However, in space or ground environment, multi-gate devices cannot yet avoid the influence of irradiation effects. Total ionizing Dose Effect (TID) mainly results in, by high-energy rays or particles, production of oxide trap charges in the oxide (such as SiO2) and production of an interface state at the oxide/silicon interface, and thereby affects a threshold voltage so that the device performance is degraded. In comparison with a conventional planar device, due to different structures, no parasitic leakage passage may be formed between a source region and a drain region in a bulk silicon multi-gate device upon total dose irradiation, whereby the bulk silicon multi-gate device is total dose radiation hardened.
Although multi-gate devices have the good performance considering TID effect, but the influence of Single Event Effect (SEE) is still very serious. For example, in an n-channel bulk silicon multi-gate device, a reverse-biased PN junction is formed around a drain region, so the drain region is sensitive to single events when the device is in off-state (where a gate voltage Vg and a source voltage Vs are at a low potential, Vd is at a high potential). The reverse-biased PN junction collects charges in a single-event ionization track and this may cause occurrence of a larger transient pulse current in the drain. When the device has a smaller size, the charges in the single-event ionization track may be collected by other sensitive nodes nearby through diffusion. Transient Pulses generated by irradiation may not be filtered during propagation, and if the pulse is propagated to a latch at an effective edge of the clock, an error information will be stored, causing the circuit state to upset. Because single-event effect is still serious in the small size of the multi-gate devices, RHBD is very important.
In the past, radiation hardening techniques are considered mostly from circuit level, such as adding filters or guard gate etc. Although the method is effective, the circuit layout area is increased by the added redundant components and the power consumption of the circuit may be increased. The layout-level hardening design can be common for the circuit such as memory cell, various hardening design methods have the respective particularities for the corresponding circuits.